The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

May. 07, 2019
Applicant:

University of Macau, Macau, CN;

Inventors:

Biao Wang, Macau, CN;

Sai-Weng Sin, Macau, CN;

Franco Maloberti, Macau, CN;

Rui Paulo da Silva Martins, Macau, CN;

Assignee:

University of Macau, Macau, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 3/00 (2006.01); H04L 27/20 (2006.01); H04B 1/00 (2006.01); H03M 1/08 (2006.01);
U.S. Cl.
CPC ...
H03M 3/454 (2013.01); H03M 1/08 (2013.01); H03M 1/12 (2013.01); H04B 1/0021 (2013.01); H04L 27/2032 (2013.01);
Abstract

An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.


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