The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Oct. 31, 2017
Applicant:

Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

David Patrick Murphy, Long Beach, CA (US);

Xiongchuan Huang, San Diego, CA (US);

Hooman Darabi, Laguna Niguel, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 3/03 (2006.01); H03L 7/081 (2006.01); H04B 1/04 (2006.01); H03L 7/183 (2006.01); H03K 5/15 (2006.01); H03L 7/099 (2006.01); H03L 7/18 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0315 (2013.01); H03K 5/15013 (2013.01); H03K 21/00 (2013.01); H03L 7/081 (2013.01); H03L 7/099 (2013.01); H03L 7/18 (2013.01); H03L 7/183 (2013.01); H03K 19/21 (2013.01); H04B 2001/0408 (2013.01);
Abstract

A circuit for providing a fractional divider/multiplier using harmonic recombination may include a power amplifier, an oscillator coupled to the power amplifier, and a divider coupled to the oscillator. In one or more implementations, the divider is configured to generate one or more phases of a harmonic from the oscillator to reduce signal interference from the power amplifier. In one or more implementations, the divider includes a divide-by-M divider, where M is a positive integer, and an array of transconductance cells coupled to the output of the divide-by-M divider. In one or more implementations, the divider includes an inductor or a filter coupled to the output of the array of transconductance cells. In one or more implementations, the oscillator includes a logical gate and a resistor-capacitor circuit coupled in series feedback with a multi-stage ring oscillator. The oscillator may include a divider coupled to the multi-stage ring oscillator.


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