The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Oct. 19, 2018
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Jong Seok Jung, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 3/012 (2006.01); H03K 3/03 (2006.01); H03K 5/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); H03K 3/0315 (2013.01); H03K 5/00 (2013.01); H03K 2005/00078 (2013.01);
Abstract

There are provided an oscillator and a memory system including the same. In the oscillator including an odd number of inverters sequentially coupled, in which an output signal of an inverter of a last stage is fed back as an input signal of an inverter of a first stage, wherein each of the inverters includes: a first input signal control unit configured to delay an input signal of each of the inverters by a first delay time or a second delay time and output a first delay input signal; a second input signal control unit configured to delay the input signal by a third delay time or a fourth delay time and output a second delay input signal; and a signal output unit configured to an output signal in response to the first delay input signal and the second delay input signal.


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