The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Oct. 28, 2016
Applicant:

Shanghai Maritime University, Shanghai, CN;

Inventors:

Tianzhen Wang, Shanghai, CN;

Zhuo Liu, Shanghai, CN;

Chao Geng, Shanghai, CN;

Jingang Han, Shanghai, CN;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 7/49 (2007.01); H02M 1/32 (2007.01);
U.S. Cl.
CPC ...
H02M 7/49 (2013.01); H02M 2001/325 (2013.01);
Abstract

The present invention discloses a voltage reference reconfiguration fault-tolerant control method for a cascaded multi-level inverter. The fault-tolerant method for the inverter automatically reconfigures the three-phase voltage amplitudes and phases of the three-phase total voltage in accordance with the fault diagnosis, thus realizing three-phase voltage balance. On the basis of the reconfiguration of the total voltage signal, re-reconfiguration of reference voltage inputted into the various H-bridges is conducted in accordance with the fault signal vectors, thereby realizing removal of the fault bridges and fault-tolerance of the normal bridges, while guaranteeing the integral sinusoidal characteristics of the actual reference voltage. The inverter realized maximum three-phase balanced line voltage in a fault occurrence, has the advantages of requiring no redundant modules and algorithms and the advantages of ease of removing fault bridges, and is applicable for reduced load operable electrical equipment.


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