The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Oct. 30, 2014
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Kuo Tung Chang, Saratoga, CA (US);

Shenqing Fang, Fremont, CA (US);

Timothy Thurgate, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11568 (2017.01); H01L 29/792 (2006.01); H01L 29/423 (2006.01); H01L 21/762 (2006.01); H01L 21/28 (2006.01); H01L 27/11521 (2017.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/76224 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/42324 (2013.01); H01L 29/792 (2013.01); H01L 29/0649 (2013.01);
Abstract

A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.


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