The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2020
Filed:
Jun. 11, 2018
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Haitao Cheng, San Diego, CA (US);
Zhang Jin, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 23/522 (2006.01); H01L 27/01 (2006.01); H01L 21/70 (2006.01); H01L 49/02 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 27/013 (2013.01); H01L 21/705 (2013.01); H01L 23/5222 (2013.01); H01L 23/5227 (2013.01); H01L 23/66 (2013.01); H01L 28/10 (2013.01); H01L 28/40 (2013.01); H01L 28/86 (2013.01); H01L 28/90 (2013.01); H01L 29/94 (2013.01);
Abstract
An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.