The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Jul. 24, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Scott K. Pozder, Saratoga Springs, NY (US);

Eng Chye Chua, Singapore, SG;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 21/66 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); G01R 31/28 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G01R 31/2884 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/522 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 23/53295 (2013.01);
Abstract

Various embodiments include monitoring structures for integrated circuits (ICs) and related monitoring methods. In some cases, a monitoring structure includes: a set of serpentine-comb structures configured to connect with a back-end-of-line (BEOL) portion of the IC, each of the serpentine-comb structures including: a chain of interconnected laterally extending wires spanning a set of metal levels in the IC; and a set of vias connecting the chain of interconnected laterally extending wires across the set of metal levels, wherein the set of vias includes at least one via spanning between each successive level of the chain of interconnected laterally extending wires, wherein the chain of interconnected laterally extending wires and the set of vias are configured to detect a chip package interface (CPI) failure in the IC.


Find Patent Forward Citations

Loading…