The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Mar. 07, 2016
Applicant:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Inventor:

Yasushi Mizusawa, Annaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B07C 5/342 (2006.01); H01L 21/66 (2006.01); C30B 29/06 (2006.01); C30B 25/20 (2006.01); G01N 21/66 (2006.01); C30B 25/02 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 22/20 (2013.01); B07C 5/342 (2013.01); C30B 25/20 (2013.01); C30B 29/06 (2013.01); G01N 21/66 (2013.01); C30B 25/02 (2013.01); H01L 27/14687 (2013.01);
Abstract

A manufacturing method of a silicon epitaxial wafer having an epitaxial layer grown on a mirror wafer of silicon, including: using a PL measuring apparatus to measure photoluminescence (PL) spectrum of the mirror wafer and adjusting the apparatus so emission intensity of a TO-line becomes 30000 to 50000 counts, irradiating the silicon epitaxial wafer with an electron beam, measuring PL spectrum from an electron beam irradiation region, and sorting out and accepting a silicon epitaxial wafer which has emission intensity resulting from a CCdefect of the PL spectrum being 0.83% or less of the emission intensity of the TO-line and from a COdefect being 6.5% or less of the emission intensity of the TO-line. The method enables sorting out a silicon epitaxial wafer which realizes a negligible level of white flaw failures in case of manufacturing an imaging element with the use of the silicon epitaxial wafer.


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