Method of generating layout and method of manufacturing semiconductor devices using same

Abstract

A method of generating a layout and manufacturing a semiconductor device, including receiving a design layout of a semiconductor device including active fins; extracting a design rule of the active fins from the design layout; forming fin lines overlapping the active fins such that the fin lines have a length that is greater than a length of the active fins, wherein the fin lines continuously extend from a position adjacent to one edge of a layout region of the semiconductor device toward another edge, and are formed in an entirety of the layout region of the semiconductor device; forming a mandrel pattern layout in an entirety of the layout region of the semiconductor device, using the fin lines; and forming a cut pattern layout in the entirety of the layout region of the semiconductor device, using the active fins.