The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Jul. 12, 2018
Applicant:

Stmicroelectronics (Tours) Sas, Tours, FR;

Inventors:

Mathieu Rouviere, Tours, FR;

Mohamed Boufnichel, Monnaie, FR;

Eric Laconde, Tours, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/3105 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30655 (2013.01); H01L 21/308 (2013.01); H01L 21/3105 (2013.01); H01L 21/78 (2013.01); B81C 2201/0112 (2013.01); H01J 2237/3341 (2013.01);
Abstract

Laterally insulated integrated circuit chips are fabricated from a semiconductor wafer. Peripheral trenches are formed in the wafer which laterally delimit integrated circuit chips to be formed. A depth of the peripheral trenches is greater than or equal to a desired final thickness of the integrated circuit chips. The peripheral trenches are formed by a process which repeats successive steps of a) ion etching using a sulfur hexafluoride plasma, and b) passivating using an octafluorocyclobutane plasma. Upon completion of the step of forming the peripheral trenches, lateral walls of the peripheral trenches are covered by an insulating layer of a polyfluoroethene. A thinning step is performed on the lower surface of the wafer until a bottom of the peripheral trenches is reached. The insulating layer is not removed.


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