The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Dec. 11, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ping Zheng, Singapore, SG;

Eng Huat Toh, Singapore, SG;

Elgin Kiok Boone Quek, Singapore, SG;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/14 (2006.01); H01L 27/112 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 17/14 (2013.01); H01L 27/11206 (2013.01); H01L 45/04 (2013.01); H01L 45/1206 (2013.01); H01L 45/146 (2013.01); H01L 45/165 (2013.01); H01L 45/1675 (2013.01);
Abstract

Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.


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