The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Mar. 24, 2017
Applicant:

Analog Devices Global Unlimited Company, Hamilton, BM;

Inventors:

Wes Vernon Lofamia, Metro Manila, PH;

Jofrey Santillan, Iligan, PH;

David Aherne, Limerick, IE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/364 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/364 (2013.01); G06F 13/404 (2013.01); G06F 13/4282 (2013.01);
Abstract

SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.


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