The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Feb. 28, 2017
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Tadaaki Tanimoto, Tokyo, JP;

Kesami Hagiwara, Tokyo, JP;

Naoyuki Morita, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2018.01); G06F 8/65 (2018.01); G06F 8/658 (2018.01); G06F 8/654 (2018.01); G06F 12/02 (2006.01); H04L 29/08 (2006.01);
U.S. Cl.
CPC ...
G06F 8/65 (2013.01); G06F 8/654 (2018.02); G06F 8/658 (2018.02); G06F 9/44521 (2013.01); G06F 12/0246 (2013.01); G06F 12/0292 (2013.01); H04L 67/34 (2013.01); G06F 2212/251 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7208 (2013.01);
Abstract

An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.


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