The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Aug. 30, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventor:

Naoya Tokiwa, Fujisawa Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 16/32 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0656 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01); G11C 7/1051 (2013.01); G11C 7/1078 (2013.01);
Abstract

A semiconductor memory includes a first plane that includes a first memory cell array, a second plane that includes a second memory cell array, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane and a second circuit configured to store a second priority for a second operation performed on the second plane, and is configured to control the first and second operations based on the first priority and the second priority. When a value of the second priority is higher than a value of the first priority, the control circuit controls the first operation such that a timing of a process executed in the first operation does not overlap with a timing of a process executed in the second operation.


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