The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Jan. 23, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Steven R. Carlough, Poughkeepsie, NY (US);

Markus Cebulla, Gerstetten, DE;

Susan M. Eickhoff, Hopewell Junction, NY (US);

Logan I. Friedman, Stamford, CT (US);

Patrick J. Meaney, Poughkeepsie, NY (US);

Walter Pietschmann, Horb-Bittelbronn, DE;

Nicholas Rolfe, Hyde Park, NY (US);

Gary A. Van Huben, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/068 (2013.01); G06F 13/1673 (2013.01); G06F 13/4282 (2013.01); G11C 7/1051 (2013.01);
Abstract

A memory system, architecture, and method for storing data in response to commands received from a host is disclosed. The memory system includes a memory control circuit configured to receive commands from the host; at least one memory device configured to store data; and at least one data buffer circuit associated with the at least one memory device and the memory control circuit, the data buffer circuit having data buffers and at least one register. The system preferably includes communication links between the host, the at least one memory control circuit, the at least one data buffer circuit, and the at least one memory device. The system preferably is configured so that register access commands are sent by the host to the memory control circuit over the communication links between the host and the memory control circuit.


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