The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Dec. 05, 2017
Applicants:

Lite-on Electronics (Guangzhou) Limited, Guangzhou, CN;

Lite-on Technology Corporation, Taipei, TW;

Inventors:

I-Hsiang Chiu, Taipei, TW;

Shih-Hung Hsieh, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/24 (2006.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 13/10 (2006.01); G06F 13/20 (2006.01); G06F 13/42 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 1/24 (2013.01); G06F 3/0601 (2013.01); G06F 13/102 (2013.01); G06F 13/1673 (2013.01); G06F 13/20 (2013.01); G06F 13/4063 (2013.01); G06F 13/4072 (2013.01); G06F 13/4295 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A solid state drive with a reset circuit includes a controlling circuit, a flash array and a buffer. The controlling circuit includes a physical layer circuit and a first input/output port. The first input/output port is connected with a first reset terminal of a host. The flash array and the buffer are connected with the controlling circuit. When the first reset terminal of the host activates a reset signal, a voltage level of the first input/output port is changed. After a delay time, the voltage level of a second reset terminal of the physical layer circuit is changed and the physical layer circuit is reset.


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