The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Mar. 28, 2019
Applicant:

Rockley Photonics Limited, London, GB;

Inventors:

Henri Nykänen, Helsinki, FI;

John Paul Drake, St. Ives, GB;

Evie Kho, Espoo, FI;

Damiana Lerose, Pasadena, CA (US);

Sanna Leena Mäkelä, Helsinki, FI;

Amit Singh Nagra, Altadena, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/26 (2006.01); G02B 6/125 (2006.01); G02B 6/136 (2006.01); G02B 6/12 (2006.01); G02B 6/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/26 (2013.01); G02B 6/12004 (2013.01); G02B 6/125 (2013.01); G02B 6/136 (2013.01); G02B 6/4214 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12104 (2013.01); G02B 2006/12176 (2013.01); G02B 2006/12178 (2013.01);
Abstract

A mirror and method of fabricating the mirror, the method comprising: providing a silicon-on-insulator substrate, the substrate comprising: a silicon support layer; a buried oxide (BOX) layer on top of the silicon support layer; and a silicon device layer on top of the BOX layer; creating a via in the silicon device layer, the via extending to the BOX layer; etching away a portion of the BOX layer starting at the via and extending laterally away from the via in a first direction to create a channel between the silicon device layer and silicon support layer; applying an anisotropic etch via the channel to regions of the silicon device layer and silicon support layer adjacent to the channel; the anisotropic etch following an orientation plane of the silicon device layer and silicon support layer to create a cavity underneath an overhanging portion of the silicon device layer; the overhanging portion defining a planar underside surface for vertically coupling light into and out of the silicon device layer; and applying a metal coating to the underside surface.


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