The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Aug. 29, 2017
Applicant:

Juniper Networks, Inc., Sunnyvale, CA (US);

Inventors:

Avi Feshali, Sunnyvale, CA (US);

John Hutchinson, Santa Barbara, CA (US);

Jared Bauters, Santa Barbara, CA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/136 (2006.01); G02B 6/122 (2006.01); G02B 6/132 (2006.01); G02B 6/32 (2006.01); G02B 6/43 (2006.01); G02B 6/12 (2006.01);
U.S. Cl.
CPC ...
G02B 6/136 (2013.01); G02B 6/122 (2013.01); G02B 6/1228 (2013.01); G02B 6/43 (2013.01); G02B 6/12002 (2013.01); G02B 6/12004 (2013.01); G02B 6/132 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12097 (2013.01);
Abstract

In integrated optical structures (e.g., silicon-to-silicon-nitride mode converters) implemented in semiconductor-on-insulator substrates, wire waveguides whose sidewalls substantially consist of portions coinciding with crystallographic planes and do not extend laterally beyond the top surface of the wire waveguide may provide benefits in performance and/or manufacturing needs. Such wire waveguides may be manufactured, e.g., using a dry-etch of the semiconductor device layer down to the insulator layer to form a wire waveguide with exposed sidewalls, followed by a smoothing crystallographic wet etch.


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