The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2020
Filed:
May. 30, 2019
Xilinx, Inc., San Jose, CA (US);
Narendra Kumar Pulipati, Hyderabad, IN;
Sree R K C Saraswatula, Hyderabad, IN;
Santosh Yachareni, Hyderabad, IN;
Weiguang Lu, San Jose, CA (US);
Fu-Hing Ho, Los Gatos, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Apparatus and associated methods relate to a consolidated power-on-reset system (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit may include a first power domain and a second power region. A level shifter circuit may be coupled to translate data from the first power domain to the second power domain. A PORS including a voltage detection circuit, a glitch filter circuit, and logic gates may be configured to generate isolation signals between the first power domain and the second power domain. The level shifter circuit may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on IC may be managed comprehensively during power-up to avoid unstable operation.