The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jul. 25, 2019
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventor:

Ikuo Soga, Isehara, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 7/04 (2006.01); H03K 7/06 (2006.01); H03K 9/04 (2006.01); H03K 9/06 (2006.01); H03K 5/00 (2006.01); H04B 1/717 (2011.01); H03L 7/08 (2006.01); H03K 5/133 (2014.01);
U.S. Cl.
CPC ...
H03K 5/00006 (2013.01); H03K 5/133 (2013.01); H03L 7/0805 (2013.01); H04B 1/7174 (2013.01);
Abstract

A pulse position modulation circuit includes a delay locked loop circuit configured to include a plurality of delay circuits coupled in a cascade, each of the plurality of delay circuits being configured to delay an input signal by a time width corresponding to a control signal so as to generate an output signal, a plurality of pulse generation circuits, each of which is configured to generate a pulse with a pulse width corresponding to a phase difference between a first signal and a second signal which have different phases from each other at different timings corresponding to states of the first signal and the second signal, each of the first signal and the second signal being the input signal or the output signal of the plurality of delay circuits, and a selection circuit configured to select pulses generated by the plurality of pulse generation circuits.


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