The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2020
Filed:
Apr. 14, 2016
Nr Electric Co., Ltd, Jiangsu, CN;
Nr Engineering Co., Ltd, Jiangsu, CN;
Zongguang Xu, Jiangsu, CN;
Jifeng Wen, Jiangsu, CN;
Yong Chen, Jiangsu, CN;
Xiang Li, Jiangsu, CN;
Yan Li, Jiangsu, CN;
Yucan Zhao, Jiangsu, CN;
Ming Yuan, Jiangsu, CN;
Qiang Zhou, Jiangsu, CN;
Guanghua Li, Jiangsu, CN;
Tianen Zhao, Jiangsu, CN;
Dewen Li, Jiangsu, CN;
NR ELECTRIC CO., LTD, Jiangsu, CN;
NR ENGINEERING CO., LTD, Jiangsu, CN;
Abstract
An apparatus and method for ensuring the reliability of a trip protection of an intelligent substation. The apparatus comprises a main CPU and an auxiliary CPU connected together, and a main FPGA and an auxiliary FPGA connected together. The main FPGA and the auxiliary FPGA are connected to a physical layer of a protection apparatus, and the main CPU and the auxiliary CPU are connected to a state monitoring data output end of a protected device. The main CPU sends a processing result to the main FPGA, the auxiliary CPU sends the processing result to the auxiliary FPGA, and the auxiliary FPGA synchronizes current information with the main FPGA after receiving information sent by the auxiliary CPU. When the main FPGA receives trip information, the main FPGA comparing the consistency of current trip information obtained from the main CPU with current trip information obtained from the auxiliary FPGA.