The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2020
Filed:
Mar. 09, 2018
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
James Karp, Saratoga, CA (US);
Michael J. Hart, Palo Alto, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/76224 (2013.01); H01L 21/76229 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0921 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823892 (2013.01); H01L 27/0928 (2013.01);
Abstract
FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the fin and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second isolation layer has a thickness greater than a thickness of the first isolation layer.