The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jan. 29, 2015
Applicant:

Hewlett-packard Development Company, L.p., Houston, TX (US);

Inventors:

Boon Bing Ng, Singapore, SG;

Lui Cheat Thin, Singapore, SG;

Reynaldo V Villavelez, Corvallis, OR (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/11517 (2017.01); H01L 27/11521 (2017.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11517 (2013.01); H01L 27/11521 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/42356 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.


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