The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jul. 25, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Seunghoon Yeon, Suwon-si, KR;

Hyoeun Kim, Cheonan-si, KR;

Jongbo Shim, Asan-si, KR;

Yonghoe Cho, Bucheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/3171 (2013.01); H01L 23/528 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01); H01L 25/105 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14517 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17134 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.


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