The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2020
Filed:
Jan. 30, 2019
Applicant:
Infineon Technologies Ag, Neubiberg, DE;
Inventors:
Stefan Kramp, Villach, AT;
Marco Koitz, Villach, AT;
Assignee:
Infineon Technologies AG, Neubiberg, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); H01L 24/06 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/0381 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/03901 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05582 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/06505 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/73207 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract
A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, a semiconductor chip includes a chip front side, a first chip pad located on the chip front side, a second chip pad located on the chip front side and an electrically insulating material located between the first chip pad and the second chip pad, wherein the first chip pad includes a surface layer predominantly comprising copper and the second chip pad includes a surface layer predominantly comprising aluminum.