The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Aug. 03, 2016
Applicant:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Inventors:

Yohei Hori, Tsukuba, JP;

Yongxun Liu, Tsukuba, JP;

Shinichi Ouchi, Tsukuba, JP;

Tetsuji Yasuda, Tsukuba, JP;

Meishoku Masahara, Tsukuba, JP;

Toshifumi Irisawa, Tsukuba, JP;

Kazuhiko Endo, Tsukuba, JP;

Hiroyuki Ota, Tsukuba, JP;

Tatsuro Maeda, Tsukuba, JP;

Hanpei Koike, Tsukuba, JP;

Yasuhiro Ogasahara, Tsukuba, JP;

Toshihiro Katashita, Tsukuba, JP;

Koichi Fukuda, Tsukuba, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 21/82 (2006.01); H01L 27/04 (2006.01); H01L 21/822 (2006.01); H01L 25/065 (2006.01); G11C 16/20 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/576 (2013.01); H01L 21/82 (2013.01); H01L 21/822 (2013.01); H01L 23/522 (2013.01); H01L 25/0657 (2013.01); H01L 27/04 (2013.01); G11C 16/20 (2013.01); H01L 23/544 (2013.01);
Abstract

A semiconductor deviceof the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits, andhaving a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.


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