The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

May. 13, 2019
Applicant:

National Tsing Hua University, Hsinchu, TW;

Inventors:

Meng-Fan Chang, Taichung, TW;

Xin Si, Hsinchu, TW;

Yung-Ning Tu, Changhua County, TW;

Jia-Jing Chen, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/418 (2013.01);
Abstract

A memory cell for computing-in-memory applications is controlled by a first bit line, a second bit line, a word line and a read word line. The read word line transmits an input value. The memory cell includes a plurality of read-decoupled cells. Each of the read-decoupled cells stores a weight and includes a first read-decoupled transistor and a second read-decoupled transistor. The first read-decoupled transistor has a first transistor width and is controlled by the weight. The second read-decoupled transistor has a second transistor width equal to the first transistor width and generates a read bit line signal according to the input value, the weight and the second transistor width. The second transistor width of the second read-decoupled transistor of one of the read-decoupled cells is two times larger than the second transistor width of the second read-decoupled transistor of another one of the read-decoupled cells.


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