The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Aug. 27, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Keiji Ikeda, Kawasaki Kanagawa, JP;

Chika Tanaka, Fujisawa Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/4096 (2006.01); H01L 27/108 (2006.01); G11C 11/4094 (2006.01); G11C 11/4074 (2006.01); G11C 11/56 (2006.01); G11C 11/4091 (2006.01); H01L 49/02 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/565 (2013.01); H01L 27/10805 (2013.01); H01L 27/10897 (2013.01); H01L 28/60 (2013.01); H01L 29/7869 (2013.01); H01L 29/78642 (2013.01);
Abstract

A semiconductor memory device includes a first memory cell that includes a first transistor and a first capacitor, a second transistor having a first terminal that is connected to a first terminal of the first memory cell, a first bit line that is connected to a second terminal of the first memory cell, a second bit line that is connected to a second terminal of the second transistor, and a controller that turns on the first transistor and turns off the second transistor during a write operation on the first memory cell and turns on the first transistor and the second transistor during a read operation on the first memory cell.


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