The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Aug. 02, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventor:

In-Woo Jun, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G06F 13/40 (2006.01); G11C 5/04 (2006.01); G11C 11/4096 (2006.01); G11C 7/02 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G06F 13/4068 (2013.01); G11C 5/04 (2013.01); G11C 7/02 (2013.01); G11C 7/1045 (2013.01); G11C 7/1048 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); G11C 2207/105 (2013.01); G11C 2207/107 (2013.01);
Abstract

A memory device including: a memory cell array; a first data input/output pin through which a first signal is input or output, wherein the first signal includes first bits to be written in the memory cell array or output from the memory cell array; a second data input/output pin through which a second signal is input or output, wherein the second signal includes second bits to be written in the memory cell array or output from the memory cell array; a first receiver configured to receive first operation codes for the first signal through the first data input/output pin; a second receiver configured to receive second operation codes for the second signal through the second data input/output pin; a first mode register configured to store the first operation codes; and a second mode register configured to store the second operation codes.


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