The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2020
Filed:
Jul. 11, 2018
Applicant:
Tc Lab, Inc., Gilroy, CA (US);
Inventor:
Harry Luan, Saratoga, CA (US);
Assignee:
TC Lab, Inc., Gilroy, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/102 (2006.01); G11C 11/39 (2006.01); H01L 27/108 (2006.01); H01L 27/105 (2006.01); H01L 29/74 (2006.01); H01L 29/87 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
G11C 11/39 (2013.01); H01L 27/1023 (2013.01); H01L 27/1027 (2013.01); H01L 27/1052 (2013.01); H01L 27/10844 (2013.01); H01L 29/0657 (2013.01); H01L 29/66363 (2013.01); H01L 29/74 (2013.01); H01L 29/87 (2013.01);
Abstract
Integrated circuit devices having multiple level arrays of thyristor memory cells are created using a stack of ONO layers through which NPNPNPN layered silicon pillars are epitaxially grown in-situ. Intermediate conducting lines formed in place of the removed nitride layer of the ONO stack contact the middle P-layer of silicon pillars. The silicon pillars form two arrays of thyristor memory cells, one stacked upon the other, having the intermediate conducting lines as common connections to both arrays. The stacked arrays can also be provided with assist-gates.