The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jan. 12, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hoi-jin Lee, Seoul, KR;

Kyoung-kuk Chae, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01); H01L 27/11807 (2013.01); H01L 27/1211 (2013.01); H01L 2027/11874 (2013.01);
Abstract

Provided is an integrated circuit. The integrated circuit includes: a first standard cell comprising a P-type Fin Field Effect Transistor (FinFET) region and an N-type FinFET region; and a filler cell adjacent to the first standard cell in a first direction and including a first region and a second region arranged in a second direction perpendicular to the first direction, wherein the first region includes a plurality of first insulating structures spaced apart from each other in the first direction, and the second region includes a second insulating structure having a width greater than that of at least one of the plurality of first insulating structures in the first direction, and one of the first region and the second region is arranged adjacent to the P-type FinFET region in the first direction and the other is arranged adjacent to the N-type FinFET region in the first direction.


Find Patent Forward Citations

Lee, Hoi-jin. (2020). Integrated circuit including filler cell (U.S. Patent No. 10635775). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10635775

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…