The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Mar. 14, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Gary James Calder, Eastleigh, GB;

Benjamin James Kerr, Overstone, GB;

Philip Rose, Oxfordshire, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01); H04L 12/741 (2013.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4204 (2013.01); G06F 13/4282 (2013.01); H04L 45/74 (2013.01); G06F 2213/0002 (2013.01);
Abstract

A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.


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