The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jan. 12, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Yusuke Shirota, Yokohama Kanagawa, JP;

Tatsunori Kanai, Yokohama Kanagawa, JP;

Masaya Tarui, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0808 (2016.01); G06F 12/0815 (2016.01); G06F 12/0831 (2016.01); G06F 12/08 (2016.01); G06F 3/06 (2006.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0808 (2013.01); G06F 3/061 (2013.01); G06F 3/065 (2013.01); G06F 3/0614 (2013.01); G06F 3/0688 (2013.01); G06F 12/08 (2013.01); G06F 12/0815 (2013.01); G06F 12/0831 (2013.01); G06F 12/0868 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/222 (2013.01); G06F 2212/312 (2013.01); G06F 2212/604 (2013.01); G06F 2212/621 (2013.01);
Abstract

According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.


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