The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Aug. 31, 2018
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Akifumi Suzuki, Tokyo, JP;

Shimpei Nomura, Tokyo, JP;

Yuto Kamo, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 3/06 (2006.01); G11C 5/04 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 3/0619 (2013.01); G06F 3/0644 (2013.01); G06F 3/0679 (2013.01); G11C 5/04 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01);
Abstract

In technique for dividing ECC large in size, plural ECCs of different sizes are required to be managed and control over storage areas of NVM is intricate. In addition, a relatively reliable page (a minimum record unit) and a relatively unreliable page are determined beforehand depending upon which recording method is adopted. However, as dispersion exists in quality among NVMs, it may occur among NVMs that dispersion in an error bit count is great among pages of the same reliability. An NVM controller in a nonvolatile memory (NVM) module divides the ECCCW into N pieces (N: two or a larger integer) of ECCCW portions and records the N pieces of ECCCW portions in N pieces of storage areas out of plural storage areas in one or more NVMs configuring an NVM section.


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