The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

Jul. 13, 2016
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Yuta Toyoda, Kawasaki, JP;

Shigeki Itou, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30174 (2013.01); G06F 9/3824 (2013.01); G06F 9/3834 (2013.01); G06F 9/455 (2013.01);
Abstract

Instruction-execution processors each execute a first instruction. A control processor converts a second instruction to be emulated into the first instruction, and enters the converted first instruction into the instruction-execution processors. In a parallel-execution period, each instruction-execution processor executes a writing-access instruction or a reading-access instruction to a memory, suspends writing of data into the memory caused by the writing-access instruction, and retains an execution history of the writing-access instruction and the reading-access instruction. The control processor selects one of instruction-execution processors in which addresses of the memory access instructions conflict with each other, causes the selected instruction-execution processor to complete the writing of the data into the memory, enters first instructions to be executed in a next parallel-execution period into the selected instruction-execution processor, and causes another instruction-execution processor to re-execute first instructions executed by the other instruction-execution processors in the parallel-execution period, in the next parallel-execution period.


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