The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

May. 07, 2018
Applicant:

Crestron Electronics, Inc., Rockleigh, NJ (US);

Inventor:

Philip Kirkpatrick, Washington, NJ (US);

Assignee:

CRESTRON ELECTRONICS, INC., Rockleigh, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04R 1/40 (2006.01); H04L 12/40 (2006.01); H04L 12/10 (2006.01);
U.S. Cl.
CPC ...
H04R 1/406 (2013.01); H04L 12/10 (2013.01); H04L 12/40136 (2013.01); H04R 2201/003 (2013.01); H04R 2420/09 (2013.01);
Abstract

A microphone array configurable to connect via an Ethernet connection with an audio processor includes a plurality of MEMS microphones (-), a plurality of sigma-delta modulators (-), a processor and storage (), and an Ethernet physical interface () operating at a network data transmission rate. Each sigma-delta modulator converts the analog output of a corresponding microphone into a bit stream at an audio sampling rate. The processor and storage performs a data-interleaving operation () to combine the bit streams from the sigma-delta modulators into a microphone audio frame serial bit stream (), and loads the microphone audio frame serial bit stream into a FIFO memory () at a FIFO serial data load rate. The processor and storage computes an Ethernet FCS checksum on the microphone audio frame serial bit stream, concatenates, an FCS delay gap, the Ethernet FCS checksum, a timing gap, a frame prefix, a UDP/IP prefix, a payload, and the microphone audio frame serial bit stream to form an Ethernet frame packet serial bit stream, unloads this Ethernet packet serial bit stream from the FIFO memory at the network data transmission rate and transmits the Ethernet frame packet serial bit stream from the Ethernet physical interface.


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