The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Jul. 26, 2019
Applicant:

Nxp B.v., San Jose, CA (US);

Inventors:

Alphons Litjes, Zijtaart, NL;

Erik Olieman, Waalre, NL;

Ibrahim Candan, Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H03M 1/468 (2013.01); H03M 1/1245 (2013.01); H03M 1/462 (2013.01);
Abstract

An integrated charge redistribution successive approximate register (CR-SAR) analog-to-digital converter (ADC) includes a sample-and-hold switch, a digital-to-analog converter (DAC), a comparator and a logic circuit. The sample-and-hold switch obtains a sample input voltage (Vin). The DAC includes a plurality of digital multiplexers that selects between a superposition phase, which superimposes an analog offset voltage onto Vin, and a conversion phase which determines values for a digital output register which determines the input values to each control line. Each digital multiplexer presents input values to a control line. The comparator has two inputs coupled to the sample-and-hold switch and to the DAC such that the output of the converter determines a value of each successive bit in the digital output register. The logic circuit is coupled to the comparator and to digital multiplexers and includes the digital output register.


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