The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Feb. 26, 2018
Applicant:

Nxp B.v., Eindhoven, NL;

Inventor:

Shufan Chan, Milpitas, CA (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 7/08 (2006.01); H02M 1/08 (2006.01); H02M 3/158 (2006.01); H03K 5/06 (2006.01); H03K 5/13 (2014.01); H03K 7/06 (2006.01); H02M 3/157 (2006.01); H02M 1/00 (2006.01); G04F 10/10 (2006.01);
U.S. Cl.
CPC ...
H03K 7/08 (2013.01); H02M 1/08 (2013.01); H02M 3/158 (2013.01); H03K 5/06 (2013.01); H03K 5/13 (2013.01); H03K 7/06 (2013.01); G04F 10/10 (2013.01); H02M 3/157 (2013.01); H02M 2001/0025 (2013.01);
Abstract

Embodiments of a constant-on-time pulse generator circuit for a DC-DC converter, a pulse width calibration circuit for a DC-DC converter, and a method for operating a constant-on-time pulse generator circuit for a DC-DC converter are disclosed. In an embodiment, a constant-on-time pulse generator circuit for a DC-DC converter includes serially connected digital buffers and a latch circuit having a set terminal, a reset terminal, and an output terminal. The set terminal and the reset terminal are coupled to the serially connected digital buffers. The latch circuit is configured to output a pulse signal with a constant pulse width through the output terminal.


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