The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Dec. 12, 2017
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Manoj Kumar, Jharkhand, IN;

Ankit Kumar, Jharkhand, IN;

Chia-Hao Lee, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 29/7881 (2013.01); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01); H01L 21/31144 (2013.01); H01L 21/32135 (2013.01); H01L 21/32139 (2013.01); H01L 27/11524 (2013.01); H01L 29/4916 (2013.01);
Abstract

A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.


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