The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Oct. 10, 2018
Applicant:

Abb Schweiz Ag, Baden, CH;

Inventors:

Chiara Corvasce, Bergdietikon, CH;

Arnost Kopta, Zürich, CH;

Maxi Andenna, Dättwil, CH;

Munaf Rahimo, Gänsbrunnen, CH;

Assignee:

ABB Schweiz AG, Baden, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/225 (2006.01); H01L 21/324 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7397 (2013.01); H01L 21/2253 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 29/0619 (2013.01); H01L 29/0696 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/402 (2013.01); H01L 29/408 (2013.01); H01L 29/66348 (2013.01);
Abstract

An IGBT is provided with at least two first cells, each of which have an n doped source layer, a p doped base layer, an n doped enhancement layer. The base layer separates the source layer from the enhancement layer, an n-doped drift layer and a p doped collector layer. Two trench gate electrodes are arranged on the lateral sides of the first cell. The transistor includes at least one second cell between the trench gate electrodes of two neighboring first cells, which has on the emitter side a p+ doped well and a further n doped enhancement layer which separates the well from the neighboring trench gate electrodes. An insulator layer stack is arranged on top of the second cell on the emitter side to insulate the second cell and the neighboring trench gate electrodes from the metal emitter electrode.


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