The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2020
Filed:
Aug. 25, 2017
Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;
Denso Corporation, Kariya-shi, Aichi, JP;
Souichi Yoshida, Matsumoto, JP;
Seiji Noguchi, Matsumoto, JP;
Kenji Kouno, Kariya, JP;
Hiromitsu Tanabe, Kariya, JP;
FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;
DENSO CORPORATION, Kariya-Shi, Aichi, JP;
Abstract
A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.