The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Sep. 08, 2017
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Shigetaka Mori, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01); H01L 29/423 (2006.01); G01R 31/28 (2006.01); H01L 29/78 (2006.01); H01L 21/66 (2006.01); G01R 31/26 (2020.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); G01R 31/26 (2013.01); G01R 31/28 (2013.01); H01L 22/34 (2013.01); H01L 29/42376 (2013.01); H01L 29/78 (2013.01); H01L 27/092 (2013.01); H01L 2027/11827 (2013.01); H01L 2027/11866 (2013.01);
Abstract

The present disclosure relates to a semiconductor device, an operation method of a semiconductor device, and a manufacturing method of a semiconductor device which are capable of minimizing influence of a gate length variation on a circuit characteristic and increasing a good product ratio (yield) in a product sorting test. A ring oscillator configured such that the plurality of inverters is connected in a ring-like form, and gate capacitors of the transistors are connected to respective output terminals of the plurality of inverters as a load capacitor outputs an oscillating signal, the ring oscillator is configured with a plurality of transistors having the same gate length, and at least two or more ring oscillators including a plurality of transistors having different gate lengths are configured. At the time of product test, the gate length is calculated on the basis of frequencies of oscillating signals of a plurality of ring oscillators, and a back bias is applied in accordance with a correction value corresponding to the calculated gate length, and an operation is performed. The present disclosure can be applied to semiconductor devices.


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