The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Nov. 07, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Nobutoshi Sugawara, Yokkaichi, JP;

Shigeyuki Sugihara, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 21/8239 (2006.01); G11C 16/04 (2006.01); H01L 27/11575 (2017.01); H01L 27/1157 (2017.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11556 (2013.01); G11C 16/0441 (2013.01); H01L 21/8239 (2013.01); H01L 27/1157 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); G11C 16/0483 (2013.01); H01L 21/823487 (2013.01);
Abstract

A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers.


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