The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Aug. 14, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yisung Hwang, Asan-si, KR;

Jungchul Lee, Cheonan-si, KR;

Jaehong Kim, Seoul, KR;

Taegyeong Chung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/46 (2006.01); H01L 21/58 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67144 (2013.01); H01L 2924/0002 (2013.01); Y10T 156/1744 (2015.01); Y10T 156/1746 (2015.01); Y10T 156/1761 (2015.01); Y10T 156/1776 (2015.01);
Abstract

An apparatus for bonding semiconductor chips may comprise transfer rails configured to transfer substrates, loading members configured to load the substrates onto the transfer rails, unloading members configured to unload the substrates from the transfer rails, a first wafer supply unit configured to supply a first wafer including semiconductor chips, and/or a bonding unit configured to bond the semiconductor chips to the substrates. An apparatus for bonding semiconductor chips may comprise a transfer rail configured to transfer substrates, loading members configured to load the substrates onto the transfer rail, unloading members configured to unload the substrates from the transfer rail, a buffer member at a side of the transfer rail configured to temporarily receive the substrates loaded by the loading members, a first wafer supply unit configured to supply a first wafer including semiconductor chips, and/or a bonding unit configured to bond the semiconductor chips to the substrates.


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