The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2020
Filed:
Nov. 09, 2016
Applicant:
Sony Corporation, Tokyo, JP;
Inventor:
Takanori Saeki, Kanagawa, JP;
Assignee:
SONY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01F 17/00 (2006.01); H01F 27/00 (2006.01); H01L 27/146 (2006.01); H01L 27/04 (2006.01); H01F 27/28 (2006.01); H01F 38/14 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01F 17/0013 (2013.01); H01F 27/2804 (2013.01); H01F 38/14 (2013.01); H01L 27/04 (2013.01); H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 28/10 (2013.01); H01F 2017/008 (2013.01); H01F 2017/0073 (2013.01); H01F 2038/143 (2013.01);
Abstract
To inhibit a decrease in inductance of an inductor in a plurality of semiconductor chips that are stacked. A semiconductor device includes: first and second semiconductor chips that are stacked; a first inductor; an arrangement-restricted region; and a circuit. In the semiconductor device, the first inductor is arranged in the first semiconductor chip. The arrangement-restricted region is provided in a region of the second semiconductor chip corresponding to the first inductor. The circuit is arranged in a region of the second semiconductor chip not corresponding to the arrangement-restricted region.