The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Apr. 15, 2015
Applicant:

Sage Design Automation Ltd., Haifa, IL;

Inventor:

Martinus Maria Berkens, Eindhoven, NL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 11/36 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G01R 31/31704 (2013.01); G06F 11/3684 (2013.01); G06F 2217/02 (2013.01); G06F 2217/06 (2013.01);
Abstract

A computer-implemented method for automated generation of test layouts for verifying a DRC deck. The method comprises receiving a first layout (L) comprising one or more polygon shapes (P) defined by a plurality of polygon parameters (W,H). Design rules (R,R) are received comprising inequality constraints (C) on the polygon parameters (W,H). A second layout (L) is calculated by applying a random change (ΔW) of value to at least one of the polygon parameters (W) of the first layout (L). A third layout (L) is calculated by varying values of the polygon parameters (W,H) of the second layout (L) until a respective slack (S,S) of the polygon parameters (W,H) with respect to one or more of the parameter boundaries (B,B) defined by the constraints is minimized. The third layout (L) may be stored as candidate test layout.


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