The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Jun. 30, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ian A. Swarbrick, Santa Clara, CA (US);

Dinesh D. Gaitonde, Fremont, CA (US);

Henri Fraisse, Sunnyvale, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/4401 (2018.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 9/4403 (2013.01); G06F 17/5009 (2013.01); G06F 2217/06 (2013.01);
Abstract

Routing a circuit design for implementation in an integrated circuit having a programmable network on chip can include determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip and generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters. A routing solution can be determined using the processor for the data flows of the circuit design by initiating execution of a SAT solver using the expression.


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