The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Dec. 25, 2017
Applicant:

Wistron Corporation, New Taipei, TW;

Inventor:

Shih-Hui Chang, New Taipei, TW;

Assignee:

Wiwynn Corporation, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/364 (2006.01); G06F 13/366 (2006.01); G06F 13/42 (2006.01); G06F 13/24 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/364 (2013.01); G06F 13/24 (2013.01); G06F 13/366 (2013.01); G06F 13/4022 (2013.01); G06F 13/4278 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is utilized for handling input/output requests of a host of the electronic system. The scheduling method includes the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to amount of the message signal interrupts corresponding to the input/output requests; and the PCIe switch handling the message signal interrupts and the read/write requests according to the scheduling sequence.


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