The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

May. 24, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Kunal Desai, Bangalore, IN;

Satyaki Mukherjee, Bangalore, IN;

Abhinav Mittal, Pune, IN;

Siddharth Kamdar, Bangalore, IN;

Umesh Rao, Bangalore, IN;

Vinayak Shrivastava, Bangalore, IN;

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0607 (2013.01); G06F 12/10 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/657 (2013.01);
Abstract

Systems, methods, and computer programs are disclosed for dynamically adjusting memory channel interleave granularity. An embodiment of a system comprises a plurality of memory clients, a memory management unit (MMU), and an address translator. The plurality of memory clients are electrically coupled to each of a plurality of memory channels via an interconnect. The MMU is configured to receive a request for a memory allocation request for one or more memory pages from one of the plurality of memory client and, in response, select one of a plurality of interleave granularities for the one or more memory pages. The address translator is configured to translate a physical address to interleave memory data associated with the one or more memory pages at the selected interleave granularity.


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