The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2020

Filed:

Mar. 21, 2016
Applicant:

Fujitsu Limited, Kwasaki-shi, Kanagawa, JP;

Inventors:

Ryohei Okazaki, Kawasaki, JP;

Norihito Gomyo, Tama, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 1/3237 (2019.01); G06F 1/3287 (2019.01); G06F 1/3234 (2019.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 1/26 (2013.01); G06F 1/3237 (2013.01); G06F 1/3243 (2013.01); G06F 1/3287 (2013.01); G06F 9/30083 (2013.01); Y02D 10/128 (2018.01); Y02D 10/152 (2018.01); Y02D 10/171 (2018.01); Y02D 50/20 (2018.01);
Abstract

An arithmetic processing device includes a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation, and a power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state. The power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.


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